The CFP1032 is a Longest Prefix Match classification processor that performs searches on Address Tables that store IPv4 addresses and their corresponding prefix lengths. Traditional methods of implementing LPM functions in a network search engine require the user to sort entries by prefix length and to leave empty spaces between prefix lengths in order to accommodate new entries. The hardware accelerated network aware architecture enables real-time updates and modifications by returning the Longest Prefix Match index regardless of its location in the Address Table. Thus the need to sort entries and to leave empty spaces is removed. New table entries are easily added at clock speed at the Next Free Address location in the table. This location is made available to the user at all times on a dedicated bus, thus maintaining coherency with the associated data.

The hardware accelerated network aware architecture significantly reduces software and hardware development time for high-end networking equipment and thus improves time-to-market. The CFP1032 is ideally suited for Layer 3 Forwarding and Next Hop Routing applications in Classless Inter-Domain Routing (CIDR).

• 32K entries; 40-bit entry width; 32-bit IPv4 address field and 8-bit user-definable field
• Clock rates: 40/50/66 MHz; sustained searches up to 66 million/second
• 40-bit I/O Bus (PBUS), 5-bit Prefix Bus (PFX), 12-bit Instruction Bus (IBUS), 40-bit Results Bus (RBUS), and 24-bit Next Free Address Bus (NFA BUS)
• Latency-invariant depth expansion without glue logic; cascadable to 256K entries.
• 2.5V Core and 3.3V I/O LVTTL, 292 PBGA package