The NL5512, NL5256, NL5128 and NL5064 devices are knowledge-based processors, which enable network awareness and provide the ability to leverage knowledge about the overall network. These knowledge-based processors provide efficient and rapid decision-making in the processing of packets, or the pieces of information flowing through the network.

The device uses information contained in single or multiple logical databases that store packet classification rules and/or IP addresses. Its primary applications are for packet classification, policy enforcement, state-based routing, packet forwarding, MPLS searches, MAC address searches and/or QoS enforcement for differentiated services in Core, Edge, Metro and Enterprise networking applications.

By providing knowledge-based processing for packets, these knowledge-based processors enable network service providers to offer more advanced functionality at wire-speed performance for the Internet, such as Voice over Internet Protocol, or VoIP, Virtual Private Networks, or VPNs, streaming video and audio, Internet Protocol version Six, or IPv6 and secure financial transactions.

Features

• NL5512 Organizations:
  • Max of 512K standard 36-bit IPv4 records
  • Dynamically configurable to 72-bit, 144-bit, 288-bit or 576-bit on a per block basis
    
    
• NL5256 Organizations:
  • Max of 256K standard 36-bit IPv4 records
  • Dynamically configurable to 72-bit, 144-bit, 288-bit or 576-bit on a per block basis
    
    
• NL5128 Organizations:
  • Max of 128K standard 36-bit IPv4 records
  • Dynamically configurable to 72-bit, 144-bit, 288-bit or 576-bit on a per block basis
    
    
• NL5064 Organizations:
  • Max of 64K standard 36-bit IPv4 records
  • Dynamically configurable to 72-bit, 144-bit, 288-bit or 576-bit on a per block basis
    
    
• 72-bit I/O Data Bus
• Support for seven independent databases
• Clock rates: 133/166/200/266 MHz
• Sustained processing rate of up to 532 MDPS for 72/144b data words (J-series)
• Each block contains eight independent Configuration Registers
• Depth cascading scheme for database expansion
• Parity Checking on I/O and Database
• IEEE 1149.1 JTAG compatible Boundary Scan
• Supply Voltages: Core: 1.0V and 1.2V
• I/Os: 1.8V and 2.5V LVCMOS, HSTL and SSTL-2 Class I & II
• Package: 529 FCBGA, 25 mm x 25 mm, 1.00 mm pitch

Device Level Block Diagram