The NL5512GLQ and NL5256GLQ devices are knowledge-based processors, which enable network awareness and provide the ability to leverage knowledge about the overall network. These knowledge-based processors provide efficient and rapid decision-making in the processing of packets, or the pieces of information flowing through the network.

These devices integrate a glue-less interface to ASICs, FPGAs and Network Processors through two QDR ™ II SRAM ports. These devices interface seamlessly to the network processors that follow the Network Processor Forum LA-1 specification including Intel's IXP2400, IXP2800 and IXP2850 and the next-generation processors from AMCC.

The device uses information contained in single or multiple logical databases that store packet classification rules and/or IP addresses. Its primary applications are for packet classification, policy enforcement, state-based routing, packet forwarding, MPLS searches, MAC address searches and/or QoS enforcement for differentiated services in Core, Edge, Metro and Enterprise networking applications.

By providing knowledge-based processing for packets, these knowledge-based processors enable network service providers to offer more advanced functionality at wire-speed performance for the Internet, such as Voice over Internet Protocol, or VoIP, Virtual Private Networks, or VPNs, streaming video and audio, Internet Protocol version Six, or IPv6 and secure financial transactions.

Features

• NL5512GLQ Organizations:
  
  • Max of 512K standard 32/36-bit IPv4 records
    
  • Dynamically configurable to 64/72-bit, 128/144-bit, or 256/288-bit on a per block basis
    
    
• NL5256GLQ Organizations:
  
  • Max of 256K standard 32/36-bit IPv4 records
    
  • Dynamically configurable to 64/72-bit, 128/144-bit, or 256/288-bit on a per block basis
    
    
• Single centralized knowledge-based processor shared across two QDRII SRAM ports
• Glue-less to network processors with NPF LA-1 compliant interfaces
• Sustained single search rate of 125 million/second on a 128-bit data word
• Interface for a general purpose Host CPU processor
• Interface for Associated Data SRAM; up to 256-bits of data returned
• Support for 128 contexts per network processor SRAM port
• Parity checking
• Dual search capability
• Depth cascading for database expansion
• Clock rates: Network Processor:
  • 250 MHz; Host CPU: 66 MHz; Associated Data SRAM: 133 MHz
    
    
• IEEE 1149.1 JTAG compatible Boundary Scan
  
• Package: 900 Flip Chip BGA, 31 mm x 31 mm, 1.00 mm pitch
  

NL5000GLQ Block Diagram