Ultra Low-Power Processor Family: Au1100®

NetLogic Microsystems’ industry-leading Alchemy® Processor family comprises a series of ultra low-power embedded processors that deliver the powerful processing performance, ultra low-power functionality and market specific integration required for next-generation products like enterprise thin clients, automotive infotainment, telematics, and other media rich embedded applications.

The NetLogic Microsystems Au1100® processor, a follow-up to the Au1000® processor, provides a high-performance, low-power, high integration chip with the inclusion of a LCD controller and further reduction in power over the Au1000. The Au1100 targets Mobile Information Appliances (IAs). These IAs include Web Pads, telematics, PDAs, and multimedia handheld computing devices.

Features

• Optimal performance at very low power
• Features highly-integrated technology including on-chip SDRAM, SRAM/Flash EPROM memory controllers, a LCD controller, 10/100 Ethernet controller, USB host and device, UARTs (3), and GPIOs (up to 48, 24 dedicated)
• Incorporation of peripherals with this very high-performance, MIPS®-compatible core can provide lower system cost, smaller form factor, lower system power requirements, simpler designs at multiple performance points, and shorter design cycles.

The NetLogic Microsystems DBAu1100 development board allows you to evaluate the operation and performance of the Au1100 processor. This highly versatile system serves multiple purposes:

• Chip evaluation
• Software development
• Example of hardware systems design using the Au1100 processor

High-Speed MIPS® CPU Core

• 333, 400 or 500MHz
• MIPS32 Instruction Set
• 32-bit Architecture
• 16KB Instruction and 16KB Data Caches
• High-speed Multiply-Accumulate (MAC) and Divide Unit
• 1.1–1.3V Core, 2.5/3.3V I/O

Highly-Integrated System Peripherals

• GPIO (48 total, 13 dedicated for system use)
• 10/100 Ethernet Controller
• USB Device and Host Controller
• Three UARTs
• IrDA Controller
• AC97 Controller
• I2S Controller
• Two Secure Digital (SD) Controllers
• Two SSI Controllers
• LCD Controller
• PCMCIA Interface Controller

On-Chip LCD Controller

• Single and Dual Panel Color
• TFT and STN Displays
• Up to 640x480 or 800x600 at 16bpp
  • Supported through Unified SDRAM-Based Frame Buffer
• Hardware Rotate for Portrait-vs-Landscape (90, 180, 270, up to 320 x 240)
• High Bandwidth Memory Buses
• 100/125MHz SDRAM Controller
  • 2.5–3.3V SDRAM Support
• SRAM/Flash EPROM Controller

Low System Power

Core MHz	Power (mW)
333	<200
400	250
500	400

• Power-saving Modes
  • Idle
  • Sleep
• Pseudo-static Design to 0Hz

Package

• 399-pin PBGA
• 17mm x 17mm

Operating System Support

• Microsoft® Windows® CE.NET
• Linux
• VxWorks

Development Tool Support

• MIPS32-compatible Tool Set
• Numerous Third-Party
• Compilers, Assemblers and Debuggers

Core Microarchitecture Highlights Pipeline

• Scalar 5-stage Pipeline
  
• Load/Store Adder in I-stage
  
• Scalar Branch Techniques Optimized
  
• Pipelined Register File Access in Fetch Stage
  
• Zero Penalty Branch

Multiply-Accumulate (MAC) and Divide Unit

• Max Issue Rate of one 32x16 MAC per Clock
• Max Issue Rate of one 32x32 MAC per Every Other Clock
• Operates in Parallel to CPU Pipeline
• Executes all Integer Multiply and Divide Instructions
• 32x16-bit MAC Hardware

MMU

• Instruction and Data Watch Registers for Software Breakpoints
  
• Separate Interrupt Exception Vector
  
• TLB
• 32 Dual-entry, Fully Associative
• Variable Page Sizes 4KB–16MB
• 4-entry ITB

EJTAG Support

Caches

• 16KB Non-Blocking Data Cache
  
• 16KB Instruction Cache
  
• Instruction/Data Caches are 4-Way Set Associative
  
• Write-Back with Read-Allocate
  
• Cache-management Features
  • Programmable Allocation Policy
  • Line Locking
  • Prefetch Instructions (instructions and data)
    
• High-speed Access to On-chip Buses