NETLNetLogic Microsystems Au1100®
Internet Edge Processor
PRODUCT BRIEF

A High-Performance / Low-Power Integrated Solution with PCI Controller
MIPS® Architecture with PCI Controller

Ultra Low-Power ProcessorOvervew
NetLogic Microsystems’ industry-leading Alchemy® Processor family comprises a series of ultra low-power embedded processors that deliver the powerful processing performance, ultra low-power functionality and market specific integration required for next-generation products like enterprise thin clients, automotive infotainment, telematics, and other media rich embedded applications.

The NetLogic Microsystems Ultra Low-Power Au1100® processor, a follow-on to the Au1000® processor, provides a high-performance, low-power, high-integration solution with the inclusion of an LCD controller and further reduction in power over the Au1000 processor. The Au1100 processor targets Mobile Information Appliances (IAs). These IAs include Web pads, telematics, PDAs, and multimedia handheld computing devices.

Product Description
The Au1100 processor delivers a complete solution based on the MIPS32® instruction set. Designed for optimal performance at a very low power, the Au1100 processor is available up to 500MHz. Power dissipation measures less than 0.25 watt for the 400MHz version. It features highly-integrated technology including on-chip SDRAM, SRAM/Flash EPROM memory controllers, an LCD controller, 10/100 Ethernet Controller, USB Host and Device, UARTs (3), and GPIOs (up to 48, 13 dedicated). In addition, the incorporation of peripherals with this very high-performance, MIPS-compatible core can provide lower system costs, smaller form factors, lower system power requirements, simpler designs at multiple performance points, and shorter design cycles.

Highlights

Our DBAu1100 development board has been designed to help Mobile IA developers:

Test processor performance
 The DBAu1100 development board is a fully integrated solution that includes both hardware and software, allowing developers to test the performance of the Au1100 processor in a variety of demanding Mobile IA applications. Rapidly develop hardware and software solutions

Rapidly develop hardware and software solutions
The DBAu1100 development board has been optimized to help customers develop hardware and software solutions based on NetLogic Microsystems’ Au1100 processor. This system incorporates an Au1100 processor, SDRAM, AMD MirrorBit™ Flash memory, and an AMD 10/100 Ethernet PHY together onto a single board, along with debug assist software (including a YAMON monitor/debugger), drivers, and design files. The result is a fully integrated system that is ready to run customer-developed software, which in turn can help reduce the development time for new Mobile IA solutions.

Learn from best practices
NetLogic Microsystems’ DBAu1100 development board is a complete hardware and software solution that serves as a model for the development of future Mobile IA solutions.

Features

High-Speed MIPS® CPU Core

  • 333, 400 or 500MHz
  • MIPS32 Instruction Set
  • 32-bit Architecture
  • 6KB Instruction and 16KB Data Caches ^pHigh-speed Multiply-Accumulate (MAC) and Divide Unit
  • 1.5–1.8V Core, 3.3V I/O

Highly-Integrated System Peripherals

  • 33/66MHz 32-bit PCI Controller (PCI 2.2 Compliant)
  • GPIO (39 total, 22 dedicated for system use)
  • Two 10/100 Ethernet Controllers
  • USB Device and Host
  • Two UARTs
  • AC97 Controller
  • PCMCIA Interface Controller

High Bandwith Memory Buses

  • Low System Power
    Core MHz Power
  • 333 <400mW 400 700mW
  • 500 1.2W
  • Power-saving Modes
    • Idle
    • Sleep
  • Pseudo-static Design to 0Hz
  • 16KB Instruction Cache

 s

Package

  • 424-pin PBGA
  • 19mm x 19mm

Operating System Support

  • Microsoft® Windows CE.NET
  • Linux
  • VxWorks

Development Tool Support

  • MIPS32-compatible Tool Set
  • 100/125MHz SDRAM Controller SRAM/Flash EPROM Controller
  • Numerous Third-Party Compilers, Assemblers and Debuggers

Core Microarchitecture Highlights Pipeline

  • Scalar 5-stage Pipeline Load/Store Adder in I-stage
  • Scalar Branch Techniques Optimized
  • Pipelined Register File Access in Fetch Stage
  • Zero Penalty Branch
  • 16KB Non-Blocking Data Cache

Internet Edge Processor

Development Tool Support

  • MIPS32-compatible Tool Set
  • Numerous Third-Party Compilers, Assemblers and Debuggers

Core Microarchitecture Highlights Pipeline

  • Scalar 5-stage Pipeline
  • Load/Store Adder in I-stage
  • Scalar Branch Techniques Optimized
  • Pipelined Register File Access in Fetch Stage

Zero Penalty Branch

Multiply-Accumulate (MAC) and Divide Unit

  • Max Issue Rate of one 32x16 MAC per Clock
  • Max Issue Rate of one 32x32 MAC per Every Other Clock
  • Operates in Parallel to CPU Pipeline
  • Executes all Integer Multiply and Divide Instructions
  • 32x16-bit MAC Hardware

 s

MMU

  • Instruction and Data Watch Registers
    for Software Breakpoints
  • Separate Interrupt Exception Vector
  • TLB
    • 32 Dual-entry, Fully Associative
    • Variable Page Sizes 4KB-16MB
    • 4-entry ITB

Caches

  • 16KB Non-Blocking Data Cache
  • 16KB Instruction Cache
  • Instruction/Data Caches are 4-Way Set Associative
  • Write-Back with Read-Allocate
  • Cache-management Features
    • Programmable Allocation Policy
    • Line Locking
    • Prefetch Instructions (instructions and data)
  • High-speed Access to On-chip Buses

Diagram

Copyright © 2010 NetLogic Microsystems, Inc. All Rights Reserved.


 

Contact Information

NetLogic Microsystems, Inc.
1875 Charleston Road
Mountain View, CA 94043, U.S.A.

Phone: +1 (650) 961-6676
Email: info@netlogicmicro.com
Web: www.netlogicmicro.com