Next Generation Multiprocessing

Overview and Benefits
The XLR500 series scalable communication processors from NetLogic Microsystems are designed to address IP networking, VoIP, wireless LAN, 3G wireless, broadband, storage, routing and switching, security, and telecommunication applications, along with the growing need to scale OEM’s software and hardware investments.

The XLR532, XLR516, and XLR508 processors integrate general purpose processing, high level programmability, scalability with thread processing, intelligent packet management, and the ability to combine control plane, data plane and security operations onto a single processor.

Based on NetLogic Microsystems’ throughput-optimized Multi-Core, Multi-Threaded architecture, the XLR532 processor integrates 32 fine-grain threads using eight MIPS64® CPU’s, the XLR516 processor integrates 16 fine-grain threads using four MIPS64® CPU’s, and the XLR508 processor integrates 8 fine-grain threads using two MIPS64® CPU’s. All three processors contain three full-speed on-chip interconnects, large multi-level caches, autonomous accelerators, quad memory controllers, and other integrated I/Os.

Each core contains 32 KBytes of Level 1 data cache and 32 KBytes of Level 1 instruction cache. In addition, the XLR532 contains 2 MB of on-chip Level 2 cache that is shared by all cores. The XLR516 contains 1 MB of Level 2 cache, and the XLR508 contains 512 KBytes of cache.

The integrated peripheral I/O of the XLR500 series allows seamless integration into current and future platforms. The quad SGMII ports (or 3 SGMII + 1 RMGII) and HyperTransport controller facilitate high throughput data connections in Advanced Telecommunications Computing Architecture (ATCA), Advanced Mezzanine Card (AMC), bladed, proprietary fabric, backplane, and standalone planar based solutions.

The combination of dense computational performance, security acceleration and network awareness makes the XLR500 series processors an exceptional solution for enhancing existing platforms, or for new developments in wired and wireless networking applications, such as content inspection, content switching, routing, load balancing, and cryptography at line rates exceeding 10Gbps.

The key to the performance and scalability of the XLR500 series processors is the Multi-Threaded CPUs coupled with NetLogic Microsystems’ Fast Messaging Network™ (FMN). Each XLR processing core contains four tightly integrated hardware threads capable of mitigating latency, improving computational efficiency and throughput. Each core has the equivalent throughput of four single threaded CPUs.

The XLR® processor family is supported by a comprehensive software development kit (SDK) that contains reference and production-ready software components, including the NetLogic Microsystems OS (Thin Executive), device drivers for open source Linux and commercial operating systems, complete tool chains, diagnostics, and the NetLogic Microsystems firmware suite. The SDK enables customers to quickly develop or migrate existing software to easily design high-performance, feature rich solutions.

Product Highlights

Next Generation Processor Cores 64-bit MIPS64® ISA with enhanced instructions Up to 8 MIPS cores, each 4-way Multi-Threaded Up to 32 fine-grain thread processing Programmable thread scheduling policies Branch Prediction and TLBs 800 MHz - 1.4 GHz operation Cache Subsystem Fully cache coherent MOSI protocol 8-way set associative architectures 32KB ECC protected L1 writeback data cache 32KB Parity protected L1 instruction cache Up to 2MB ECC protected banked writeback L2 cache High Speed Distributed Interconnects High-speed core frequency non-blocking Data Interconnection Ring connect all cores, caches, memory, acceleration engines, and I/O 10 simultaneous memory transactions per clock Non-blocking split transaction operations Fast Messaging Network™ passes/transmits packet descriptor and control messages among CPUs, acceleration engines and I/Os. Leading Edge Security Engine Up to 11.6 Gbps of bulk encryption / decryption Up to 4 high-speed crypto engines Kasumi, DES/3DES, AES/AES-GCM, ARC4 (128, 192, 256) MD5, SHA-1, SHA-256 (All HMAC) DH and RSA Exponentiation Random number generator Networking Hardware Accelerator Packet Distribution Engine® for line rate processing Packet ordering assists TCP checksum verification / generation

General Purpose Programming Virtual MIPS ® mode isolates cores and enables virtualization of unmapped memory regions Supports both clustered and SMP modes 3 fine and coarse grained scheduling modes / CPU Supports parallel, pipelined, and hybrid processing modes On-chip debug support with performance monitoring Integrated System Interfaces PCMCIA interface Flash memory interfaces Dual I 2 C interfaces Dual 16550 UART interfaces 32-bit GPIO interface IEEE 1149.1 JTAG and BIST functionality High Performance Memory Controllers Quad DDR2 DRAM controllers with nibble error correction 4x36 or 2x72 mixed memory use per x72 DRAM channel 4-channel DMA controller with built in CRC generation Extensive Networking and I/O Interface Options Four 10/100/1000 RGMII Packet distribution and order sequencing hardware PCI-X - 64/32-bit 133-MHz (PCI 2.2) master or target HyperTransport - 8-bit, 3.2 GB/s with PIC Power Management Dynamic clocking control On-chip thermal sensor Software programmable clock throttling

Product Availability

The XLR532, XLR516, and XLR508 processors are available in a RoHS-compliant 1605 BGA package. There are different power grades (standard, low power and ultra low power) as well as commercial and industrial operating temperatures. The XLR500 series processors are pin compatible. Each of these products are also pin compatible with the XLR700 series of processors.

Also available from NetLogic Microsystems are evaluation platforms for the entire product family.

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Block Diagram

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Application Examples