Next Generation Multiprocessing

Overview and Benefits
The XLS404 processor from NetLogic Microsystems® offers the industry’s firstMulti-Core, Multi-Threaded processor with integrated Serial RapidIO interface support and IEEE1588-compliant precision timing protocol (PTP) controller, making it an ideal solution for next-generation wireless designs.

The XLS404 provides system designers with pin-compatible upgradeability from the previously announced members of the XLS processor family. The XLS404 processor leverages the original XLR® series performance, scalability and innovation while extending software compatibility throughout both product families and addressing applications where PCB real estate and power are premiums.

The XLS404 supports a rich set of features and integration with unprecedented power/performance for embedded communication and telecommunication, enterprise wireless and wired-line LAN, and SMB networking applications. These solutions include 3G/WiMAX/LTE base stations, integrated security appliances, wireless Access Points and switches, ATCA and AMC service cards, secured wire-line routers and switches, telecom media gateways, radio controllers and network signaling equipment.

The XLS404 processor integrates general-purpose processing, high level programming, scalability with thread processing, intelligent packet management, and the ability to combine control plane, data plane and security operations on a processor built on advanced submicron silicon technology.

Based on NetLogic Microsystems’ throughput-optimized Multi-Core, Multi-Threaded architecture, the XLS404 processor integrates up to 4 fine-grain processing threads (using single-clock thread context switching) from a single MIPS64 CPU. Threading overcomes processor stalls common to scalar or superscalar (multi-issue) CPUs when processing packets in networking environments. The XLS processor core contains four tightly coupled hardware threads capable of hiding latency, improving computational efficiency and throughput. The Fast Messaging Network (FMN) eliminates performance robbing semaphores and spinlocks found in multi-processor architectures and system loading due to intra-packet movement by supporting billions of in-flight messages and packet descriptors between all on-chip elements.

Additional features include large multi-level caches, autonomous security and compression accelerators, quad memory controllers, eight Gigabit Ethernet MACs supporting S/RGMII or XAUI, PCI-Express or SRIO, and GPIO. The integrated peripheral I/O allows seamless integration in both today’s and next-generation platforms. The PCIe and SRIO controllers and the octal network ports with IEEE1588-compliant PTP control facilitates high throughput data connections in ATCA, AMC, bladed, proprietary fabric, backplane, and standalone planar based solutions.

Product Highlights

Next Generation Processor Cores 64-bit MIPS64 ISA with enhanced instructions Core supports 4-way multi-threading Fine-grain processing of 4 threads Programmable thread scheduling policies Branch Prediction and TLBs 800MHz, 1GHz or 1.2GHz operation Cache Subsystem Fully cache-coherent MOSI Protocol 8-way set-associative architectures L1 DedicatedPlus Cache per thread allocation 32KB ECC-protected L1 writeback data caches 32KB parity-protected L1 instruction 512 KB ECC-protected banked writeback L2 caches High Speed Distributed Interconnects Connects MIPS core, caches, I/O and processing agents 6 simultaneous memory transactions per clock Throughput-optimized split transaction operations Fast Messaging Network™ for communication between processing and I/O Leading Edge Autonomous Accelerators Up to 2.5Gbps of bulk encryption / decryption Kasumi, DES/3DES, AES/AES-GCM, ARC4 (128, 192, 256) MD5, SHA-1, SHA-256/384/512 (All HMAC) RSA, DH and ECC Exponentiation and Multiplication Up to 2.5Gbps of Compression/Decompression ZLIB/Deflate/GZIP (RFC1950/1/2), 32KB Dictionary Size Networking Hardware Acceleration Packet distribution engine for line rate processing Packet ordering assists TCP checksum verification / generation

General Purpose Programming Virtual MIPS mode enables virtualization of unmapped memory region Supports both clustered and SMP modes Supports parallel, pipelined, and hybrid processing modes On-board debug support; performance monitoring Integrated System Interfaces PCMCIA interface Bootable NAND Flash memory interface Dual I2C interfaces Dual 16550 UART interfaces 32-bit GPIO interface IEEE 1149.1 JTAG and BIST functionality High Performance Memory Controllers Dual DDR2 DRAM controllers Advanced nibble error correction 1 x36 bit or 1 x72 bit mixed memory use 4-channel DMA controller with built-in CRC generation Extensive Networking and I/O Interfaces Eight 10/100/1000 Ethernet MACs (8 SGMII, or 7 SGMII plus 1 RGMII) Packet distribution and order sequencing hardware PCIe 1.1 controller supporting 4 x1 or 1 x4 lane configurations PCIe interface can be optionally configured as SRIO Dual USB 2.0 ports; host and client modes Power Management Dynamic Clocking control On-chip thermal sensor Software-programmable clock throttling

Product Availability

The XLS404 is available in RoHS-compliant BGA packaging and supports 800MHz, 1GHz and 1.2GHz operating frequencies at industrial (100°C) operating temperatures.

The XLS Processor family is supported by a comprehensive software development kit (SDK) which contains reference and production-ready software components, including the NetLogic MicrosystemsOS accelerated wire-level OS, device drivers for open source Linux and commercial OS, complete tool chains, diagnostics, and the NetLogic Microsystems firmware suite. The SDK enables customers to quickly develop or migrate existing software to design high-performance, feature-rich solutions with ease.

Also available from NetLogic Microsystems are several evaluation platforms designed to allow customers to evaluate the entire product family’s integrated features and perform application tests in parallel with hardware development.

---

Block Diagram

---

Application Examples