Next Generation Multiprocessing

Overview and Benefits
The XLS608 processor from NetLogic Microsystems expands on the success of the XLR processor® product line by offering a mid-level derivative version of the Multi-Core, Multi-Thread architecture, making it an ideal solution for next generation designs. The XLS608 leverages the XLR’s performance, scalability and innovation while extending software compatibility throughout both product families and addressing applications where PCB real estate and power are premiums.

The XLS608 supports a rich set of features and integration with unprecedented power/performance for the embedded communication and telecommunication, enterprise wireless and wired-line LAN, and SMB networking applications. These solutions include integrated security appliances, wireless Access Points and switches, ATCA and AMC service cards, secured wire-line routers and switches, telecom media gateways, radio controllers and network signaling.

The XLS® processor integrates general-purpose processing, high level programming, scalability with thread processing, intelligent packet management, and the ability to combine control plane, data plane and security operations on a single processor built on advanced sub-micron silicon technology.

Based on NetLogic Microsystems’ throughput-optimized Multi-Core, Multi-Threaded architecture, the XLS608 processor integrates up to 8 fine-grain processing threads (using single-clock thread context switching) from two MIPS64 CPUs. Threading overcomes processor stalls common to scalar or super-scalar (multi-issue) CPUs when processing packets in networking environments.

Additional features include three high speed on-chip interconnects, large multi-level caches, autonomous security and compression accelerators, quad memory controllers, eight Gigabit Ethernet MACs providing SGMII and RGMII support, PCI-Express, and GPIO. The integrated peripheral I/O allows seamless integration in both today’s and next-generation platforms. The PCIe controllers and the octal network ports facilitate high throughput data connections in ATCA, AMC, bladed, proprietary fabric, backplane, and standalone planar based solutions.

Each XLS processing core contains four tightly integrated hardware threads capable of hiding latency, improving computational efficiency and throughput. One XLS processing core has the equivalent throughput of up to four single threaded CPUs. The Fast Messaging Network™ (FMN) eliminates performance robbing semaphores and spin-locks found in multi-processor architectures and system loading due to intra-packet movement by supporting billions of in-flight messages and packet descriptors between all on-chip elements. These are just several of the many advanced technologies found in the XLS processor family.

The XLS Processor family is supported by a comprehensive software development kit (SDK) which contains reference and production-ready software components, including the NetLogic Microsystems OS accelerated wire-level OS, device drivers for open source Linux and commercial OS, complete tool chains, diagnostics, and the NetLogic Microsystems firmware suite.

Product Highlights

Next Generation Processor Cores 64-bit MIPS64 ISA with enhanced instructions 2 cores - each 4-way Multi-Threaded Fine-grain processing of 8 threads Programmable thread scheduling policies Branch Prediction and TLBs 800MHz, 1GHz or 1.2GHz operation Cache Subsystem Fully cache-coherent MOSI Protocol 8-way set-associative architectures L1 DedicatedPlus Cache® per thread allocation 32KB ECC-protected L1 writeback data caches 32KB parity-protected L1 instruction 1MB ECC-protected banked writeback L2 cache High Speed Distributed Interconnects Connects all cores, caches, I/O and processing agents 6 simultaneous memory transactions per clock Throughput-optimized split transaction operations Fast Messaging Network™ for communication between processing and I/O Leading Edge Autonomous Accelerators Up to 2.5Gbps of bulk encryption / decryption Kasumi, DES/3DES, AES/AES-GCM, ARC4 (128, 192, 256) MD5, SHA-1, SHA-256/384/512 (All HMAC) RSA, DH and ECC Exponentiation and Multiplication Up to 2.5Gbps of Compression/Decompression ZLIB/Deflate/GZIP (RFC1950/1/2), 32KB Dictionary Size Networking Hardware Acceleration Packet Distribution Engine® for line rate processing Packet ordering assists TCP checksum verification / generation

General Purpose Programming Virtual MIPS Mode isolates cores and enables virtualization of unmapped memory region Supports both clustered and SMP modes Supports parallel, pipelined and hybrid processing modes On-board debug support; performance monitoring Integrated System Interfaces PCMCIA interface Bootable NAND Flash memory interface Dual USB 2.0 ports; Host and Client Modes Dual I2C interfaces Dual 16550 UART interfaces 32-bit GPIO interface IEEE 1149.1 JTAG and BIST functionality High Performance Memory Controllers Quad DDR2 DRAM controllers Advanced nibble error correction 4 x36 or 2 x72 mixed memory use per 72-bit DRAM channel 4-channel DMA controller with built-in CRC generation Extensive Networking and I/O Interfaces Eight 10/100/1000 Ethernet MACs (8 SGMII, or 7 SGMII plus 1 RGMII) Each group of 4 MACs can be optionally configured as a XAUI port Packet distribution and order sequencing hardware PCIe 1.1 controller supporting 4 x1 or 1 x4 lane configurations PCIe interface can be optionally configured as SRIO Power Management Dynamic Clocking control On-chip thermal sensor Software-programmable clock throttling

The SDK enables customers to quickly develop or migrate existing software to design high-performance, feature-rich solutions with ease.

Product Availability

The XLS608 is available in RoHS-compliant BGA packaging and supports 800MHz, 1GHz and 1.2GHz operating frequencies at industrial (100°C) operating temperature.

Also available from NetLogic Microsystems are several evaluation platforms designed to allow customers to evaluate the entire product family’s integrated features and perform application tests in parallel with hardware development.

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Block Diagram

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Application Examples