Puma AEL1010
10GbE/10GFC LAN/WAN PHY/SerDes

NetLogic Microsystems' Puma AEL1010 device is a WAN Interface Sublayer (WIS) – enhanced physical layer transceiver designed for use in LAN/WAN/SAN XFP and limiting SFP+ linecard applications. It integrates the SerDes/PHY capabilities of NetLogic Microsystems’ Puma AEL1001 device with a full implementation of the IEEE 802.3ae WIS function, allowing transmission of 10 Gigabit Ethernet traffic across SONET-based optical networks.

The AEL1010 device uses NetLogic Microsystems’ high-density PHY technology to offer an attractive combination of high performance (10 Gbps) and low power consumption. Full PCS, PMA, and XGXS sub-layer functionality is provided through the consolidation of the receiver and transmitter PHY functions on a single chip along with the integration of encode/decode/alignment logic, FIFOs, on-chip clock drivers, multiple loop-back features and PRBS generation & verification for both the line side and the system side.

To enable the optional WIS support, the AEL1010 device includes clocking modifications allowing support for the 10 Gigabit Ethernet data rates of 10.3125 Gbps and the SONET data rate of 9.953 Gbps in an implementation requiring only a single external clock input - which could be either an XO or a VCXO. In both cases SONET-grade jitter transfer compliance is achieved, while the integrated WIS digital block meets the requirements of clause 50 of the IEEE 802.3ae standard.

Benefits

• Low power dissipation enables smaller 10G optical modules – XFP and limiting SFP+ linecards
• Low power dissipation enables higher levels of integration on linecards
• AEL1001/AEL1006 pin-compatible
• Meets IEEE XAUI Jitter Tolerance specifications
• Integrated limiting amplifier improves receive sensitivity
• Reference Clock clean-up circuit allows loop timing capability in WAN mode
• Enhanced BIST features simplify optical modules testing
  
  

Features

• Best-in-class power consumption
• On-chip clock generation and data recovery
• Integrated clock synthesizer for operating with a single clock source
• Integrated limiting amplifier
• Programmable bit and lane ordering
• Adjustable XAUI transmit pre-emphasis
• Jumbo frames supported
• Multiple loop-back modes
• Packet, PRBS, CJPAT and CRPAT generators and checkers
• MDIO, JTAG & SDA/SCL physical interfaces
• 144 pin, 13x13mm, 1mm ball pitch PBGA package
• Low latency of 120ns

Applications

• 10 Gigabit Ethernet LAN/MAN/SAN Systems
• 10 Gigabit Fibre Channel SAN Applications
• 10GbE Add/drop Multiplexers
• 10GbE Switch/router Backbones
• 10GbE Hubs and Repeaters
• 10GbE/10Gb FC Test Equipment
• 10GbE Terabit Routers
• 10GbE NICs
• 10Gb FC HBAs

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