NetLogic Microsystems' Puma AEL3005 device is a physical layer transceiver designed for 10GBASE-KR (IEEE802.3ap) backplane applications with an integrated Forward Error Correction (FEC) function, Electronic Dispersion Compensation (EDC) engine and 3-tap TX pre-emphasis on the 10G side. The device integrates NetLogic Microsystems' industry-leading SerDes/PHY technology from the earlier generation of 10G PHY/SerDes devices (XAUI to 10G) with an innovative low-power FEC function.

The FEC implementation includes an encoder/decoder function that conforms with the 10GBASE-KR backplane (802.3ap) standard; which includes 64/66 to 64/65 transcoding, followed by encoding using the length (2112,2080) shortened cyclic code prescribed in the 802.3ap standard. The FEC implementation is achieved with low decoder latency (only 20ns extra) and low power dissipation. Additionally, there are several enhanced error statistics reporting functions included (ex. separate 0s and 1s error statistics; data pattern matching and error pattern matching with programmable settings)

Benefits

• The 10x10mm QFN is the industry’s smallest integrated FEC/EDC/PHY/SerDes and making it ideal for use in dense backplane applications
• High performance FEC function that allows for up to 40inches of FR4 trace length for large backplane applications
• Low power-dissipating backplane SerDes device allows dense backplane architectures
• Low-latency FEC implementation adds only 20ns to the single frame delay required by all decoders
• Enhanced error statistics like data pattern matching and error pattern matching with programmable settings are useful for analyzing system performance and tuning overall system settings
• Enhanced BIST features simplify system-level link testing