Puma NLP3040
Quad 10GbE LAN PHY KR SerDes

NetLogic Microsystems' Puma NLP3040 device is a quad physical layer transceiver with an integrated Electronic Dispersion Compensation (EDC) engine - compliant with IEEE802.3ap specifications. The device incorporates NetLogic’s next generation industry-leading SerDes/PHY technology after the success of its earlier generation of 10G PHY/SerDes devices (AEL1001 – 1006). The device includes a start-of-the-art low-power EDC engine targeted for 10GBASE-KR and SFP+ direct attach copper applications.

The NetLogic Microsystems Puma NLP3042 device provides full PCS, PMA, and XGXS sub-layer functionality through the consolidation of the receiver and transmitter PHY functions on a single chip along with the integration of encode/decode/alignment logic, FIFOs, on-chip clock drivers, multiple loop-back features and PRBS and Ethernet frame generation & verification for both the line side and the system side.

Benefits

• EDC/PHY/SerDes – making it ideal for use in dense applications
• High performance EDC engine for KR grade performance
• EDC and pre-emphasis functions allow for up to 15 m of twin-ax copper cable transmission
• Low latency and low power dissipation makes it ideal for use in datacenter Ethernet applications
• Enhanced BIST features simplify optical modules testing
  

Features

• Best-in-class power consumption
• XAUI system side interfaces
• On-chip clock generation and data recovery
• Capable of operating with 50 MHz reference clock
• TX pre-emphasis and RX equalization on the XAUI interface
• KX capability
• Adjustable XAUI transmit pre-emphasis
• Multiple loop-back modes
• Packet, PRBS, CJPAT & CRPAT generators & checkers
• MDIO, JTAG & SDA/SCL physical interfaces
• RoHS 5/6 and RoHS 6/6
• Low latency of 120ns

Applications

• With KR Backplane Blade Server Applications
• With direct-attached copper SFP+ Applications
• High Density Datacenter Ethernet Applications
• Aggregation switches that need 40GE backplane links

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